Personal projects, including mini-projects, that I have contributed to and for which I have permission to share publicly are included in this repository. Small descriptions are also included for convenience.

The University of Manitoba chapter of the Institute of Electrical and Electronics Engineers (UMIEEE) holds many workshops for both chapter members and non-members. However, an issue presented itself where there was no effective manner to analyze the registration information for auditing purposes. extractor.py, using Python's argparse library allowed to set flags to pull specific basic data points from all registrations or a subset of registrations.

Using Verilog, Quartus II Prime Software, and the DE10-Standard FPGA-SoC Development Board, a digital stopwatch with lap view capabilities was implemented. The stopwatch was designed to be accurate to two decimal places.