1. Pull and run Tensil docker container (see below);
2. Download and install Xilinx Vitis or Vivado;
3. Download and install Xilinx PYNQ for your FPGA development platform;
4. Copy Tensil PYNQ driver drivers/tcu_pynq to /home/xilinx/tcu_pynq on your FPGA development platform.

docker pull tensilai/tensil
docker run -v $(pwd):/work -w /work -it tensilai/tensil bash

Compile AI/ML model (ResNet20 v2 CIFAR) for specific TCU architecture and FPGA development platform (Avnet Ultra96 v2).

tensil compile -a /demo/arch/ultra96v2.tarch -m /demo/models/resnet20v2_cifar.onnx -o "Identity:0" -s true

tensil compile -a /demo/arch/ultra96v2.tarch -m /demo/models/resnet20v2_cifar.pb -o "Identity" -s true

• TensorFlow and Tflite
• Pytorch
• Other

Make Verilog RTL for specific TCU architecture and FPGA development platform (Ultra96 v2) and 128-bit AXI interface to DDR memory.

tensil rtl -a /demo/arch/ultra96v2.tarch -d 128 -s true

Create Vivado design for specific FPGA development platform (Ultra96 v2). If this is something you don't know how to do, we can help! Please reach out to us at [email protected].

Use PYNQ and Jupyter notebooks to run AI/ML model on FPGA. (See in notebooks.)

1. Download and install OpenJDK 11 from Azul;
2. Download and install Verilator;
3. Download test models:

wget https://github.com/tensil-ai/tensil-models/archive/main.tar.gz
tar xf main.tar.gz
mv tensil-models-main models
rm main.tar.gz

./mill rtl.run -a ./arch/ultra96v2.tarch -d 128 -s true

./mill tools.run -a ./arch/ultra96v2.tarch -m ./models/resnet20v2_cifar.onnx -o "Identity:0" -s true

./mill __.test -l org.scalatest.tags.Slow

• Say hello and ask a question on our Discord
• Email us at [email protected]