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f4pga-database-visualizer

f4pga-examples

Example designs showing different ways to use F4PGA toolchains.

f4pga-rr-graph

Collection of Routing Resources Graph (RR Graph) libraries for VPR

f4pga-sdf-timing

Python library for working Standard Delay Format (SDF) Timing Annotation files.

f4pga-v2x

Tool for converting specialized annotated Verilog models into XML needed for Verilog to Routing flow.

f4pga-xc-fasm

f4pga-xc-fasm2bels

Library to convert a FASM file into BELs importable into Vivado.

f4pga-xc7-bram-patch

Tool for updating the contents of BlockRAMs found in Xilinx 7 series bitstreams.

fasm

FPGA Assembly (FASM) Parser and Generator

firrtl

Flexible Intermediate Representation for RTL

firrtl-spec

The specification for the FIRRTL language

foundation

Governance-related CHIPS Alliance documents, guides etc.

fpga-interchange-schema

fpga-interchange-tests

Repository to run extensive tests on the FPGA interchange format

fpga-tool-perf

FPGA tool performance profiling

homebrew-verible

ideas

omnixtend

OmniXtend cache coherence protocol

playground

chipyard in mill :P

presentations

python-fpga-interchange

Python interface to FPGA interchange format

riscv-dv

Random instruction generator for RISC-V processor verification

riscv-fw-infrastructure

SDK Firmware infrastructure, contain RTOS Abstraction Layer, demos, SweRV Processor Support Package, and more ...

riscv-v-spec

Working draft of the proposed RISC-V V vector extension

rocket

The working draft to split rocket core out from rocket chip

rocket-chip

Rocket Chip Generator

rocket-chip-blocks

RTL blocks compatible with the Rocket Chip Generator

rocket-chip-fpga-shells

Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards

rocket-chip-inclusive-cache

An RTL generator for a last-level shared inclusive TileLink cache controller

rocket-pcb

PCB libraries and templates for rocket-chip based FPGA/ASIC designs