The DTACK logic in the CPLD needs to be updated to conditionally assert DTACK for on-board memories and peripherals only. Currently is always drives DTACK low except for the case when a UM245R access is pending and the USB FIFO state prohibits it.

This came up when the SBC PIO board's wait state selection circuit seemed to have no effect. Probably easiest way is to OR all the chip enables together to make a unified "assert DTACK locally" signal. May need to change some things depending on remaining CPLD resources, it's pretty full as-is.

On the flip side this proves everything is working in a stable state at full speed with the system running at 10/12 MHz which is excellent.

Some debug code was enabled that left interrupt-driven reception and polling transmission enabled. Switching to interrupt driven transmission resulted in slower data rates for some reason.

Look into: check TXRDY vs TXEMT, how soon a TXRDY interrupt happens after setting IMR to 0x05 after inserting a byte into the ring buffer, etc.

Add some resource locking so the polling and non-polling routines can co-exist.

Current application projects use SysGCC from https://gnutoolchains.com/
The earlier boot ROM was written using SGDK and needs to be moved over to these tools for consistency.