FPGA alarm clock system

Design and implementation of an FPGA-based Alarm Clock using VHDL in Quartus Prime software targeted for Intel MAX 10 FPGA. The alarm clock can set the time, set an alarm time, snooze, and reset. An LED will turn on when the time reaches the alarm and will turn off when the user presses the snooze switch. The time is displayed in the military time format using seven segment displays. The entire project was soldered onto a PCB.