c-l-g Goto Github PK
Name: Chinese-Logic-Group
Type: Organization
Bio: FPGA**开源组织
Name: Chinese-Logic-Group
Type: Organization
Bio: FPGA**开源组织
altera video DMA
AXI 总线验证 模块
Cordic 算法实现
数据统计直方图
组织文档
mini FIFO verilog script
图像文件读取仿真库
通用Cordic旋转模块
:statue_of_liberty:最新可用的google hosts文件。镜像:
IIC I2C Master
求解线性方程组
线性映射,线性函数拟合,verilog,
线性方程,就是一个3x3的矩阵乘以一个1x3的向量
auto_generate script of TCL for modelsim
本地迷你的hdl代码版本控制
根据最近看的一本书编写的对应RTL以及Testbench
牛顿迭代 除法
dynamic configuration for pll ,just altera (PLL动态配置模块,仅适用于 Altera)
通用的公共小模块
unsigned Radix-2 SRT division,基2除法
rgb和lab互转
RGB 和 YCbCr 高精度互转
视频RGB转YUV格式
尝试构造新的硬件描述语言
脚本参考,包括shell perl tcl等
随机数生成模块
排序 verilog 实现
SPI model for similation
SPI-PHY RTL
通过spi配置寄存器
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