Caterpillar is a C++-17 library dedicated to the synthesis of large quantum circuits implementing Boolean functions, with a focus on quantum memory management. Read the full documentation.
The following code reads an XAG network from a verilog file and uses logic network based synthesis to obtain the corresponding reversible circuit. In this example, we use the pebbling mapping strategy, that is a SAT-based method enabling constraints on the number of qubits.
/* read verilog file using lorina */
mockturtle::xag_network xag;
auto const result = lorina::read_verilog( "ex.v", mockturtle::verilog_reader( xag ) );
if ( result != lorina::return_code::success )
return 0;
/* select the pebbling compilation strategy */
caterpillar::pebbling_mapping_strategy_params ps;
ps.pebble_limit = 100;
caterpillar::pebbling_mapping_strategy<mockturtle::xag_network> strategy( ps );
/* compile to quantum circuit */
tweedledum::netlist<caterpillar::stg_gate> circ;
caterpillar::logic_network_synthesis( circ, xag, strategy);caterpillar is part of the EPFL logic synthesis libraries. The other libraries and several examples on how to use and integrate the libraries can be found in the logic synthesis tool showcase.
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