Contains all of the projects from both Digital Logic Design and Digital Logic Design Lab courses.

Each project comes with a manual which explains the project and its goals in great detail. The Lab projects are much more advanced and require more effort!

The project titles are as below:

• CA1: Basic Switch and Gate Structures in Verilog
• CA2: Basic Switch and Gate Structures in Verilog
• CA3: Small-Scale RT Level Components, Iterative Logic
• CA4: Basic Memory Structures, Latches and Flip-Flops
• CA5: Counters, Shifters, State Machines
• CA6: RTL Complete Component Design

• CA1: Clock and Periodic Signal Generation
• CA2: Clock Adjusting and Monitoring
• CA3: Function Generator
• CA4: Integrated System