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ucr-eecs168-lab's Introduction

eecs168 - Introduction to VLSI Design

Lab Resources

Every discussion/Q&A will be at https://github.com/sheldonucr/ucr-eecs168-lab. Please use GITHUB page instead of email to ask any questions to TA. Questions of confidential nature, eg. grading, are the exception. Labs must be finished on the given time. You have one week for your lab report. Lab due dates are indicated in the Lab schedule. Your lab will be due on your respective lab day, eg. if your lab day is Wednesday then you will turn in your lab on the Wednesday of the week your lab is due. Please be sure to include all required deliverables in your lab report. Five lab reports are required to turn in and total score is 100. Team work (Pair design and programming) (limit 2) is allowed but individual lab report is required and those lab reports should not be the same with your pair.

Lab schedule

Week Date Remark Description Points
Week 1 Pre-Lab - ENGR account checkup / Linux System Basic
Week 2 Lab/Tutorial 1 - Synopsys Schematic Design (Galaxy Custom Designer)/ Pre-Simulation (HSPICE) 10
Week 3 Lab/Tutorial 2 - Synopsys Layout Design (Galaxy Custom Designer) / Design Rule Check (DRC) / Verification (LVS) Lab1 report due by the end of lab 15
Week 4 Lab/Tutorial 3 - Post-Simulation with Parasitic Extraction (HSPICE). Simple Hierarchical IC Design (Target Circuit: Ring Oscillator) Lab2 report due by the end of lab. 40
Week 5 Lab/Tutorial 3 - Hierarchical IC Design (Target Circuit: 1-bit full adder-no hierarchical design)
Week 6 Lab/Tutorial 3 - Hierarchical IC Design (Target Circuit: 4-bit full adder-use Hierarchical)
Week 7 Lab3 work week. No new assignment. Lab3 report due by the end of lab.
Week 8 Lab/Tutorial 4 - RTL Synthesis Design (Design Compiler/IC Compiler/PrimeTime) (Target Circuit: 4-bit full adder) 35
Week 9 Lab/Tutorial 4 - Complex RTL Synthesis Design (Target Circuit: Euclid's Algorithm for GCD)
Week 10 Lab/Tutorial 4 - Full Chip RTL Synthesis Design (Target Circuit: Core Design)
Final Week No lab Lab4 report due by Monday.

Attendance Policy

  • Late, which are after (11:10am for Wednesday, 5:10pm for Friday) will be 10% penalty
  • More than 10min late, which are after (11:20am for Wednesday, 5:20pm for Friday) will be 50% penalty
  • Missing a lab is acceptable only for emergency (eg. Medical emergency, doctor letter is required) and should be completed within 1 week of the missed lab.
  • Labs can be skipped by completing early. Proof of completion will be due prior to the start of your scheduled lab day, eg. before 11:10am for Wednesday labs, 5:10am for Friday labs. Available by request ONLY.

Late Submission for lab report

  • Late submission will not be accepted for your lab report.

Checkoff

  • You need to get checkoff your each lab result. If not , you will receive no credit for your lab score even if you submit your lab report. Checkoff means showing your completed work to your TA.

Cheating Policy

Each lab report should be individual even if you can do pair design and programming. If I find students cheating on the lab report, I give no credit for lab given report. Then I forward your case to the academic integrity board at UCR.

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