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c2a-core's Introduction

Core of Command Centric Architecture

C2A

  • Command Centric Architecture
  • OBC 搭載フライトソフトウェアフレームワーク
  • v4 系以降の先行開発は https://github.com/arkedge/c2a-core で行われる

C2A core

  • 各 C2A で共通利用される C2A の中核部のコード
  • 基本的には，各々の C2A user repository （サンプル： TBW） にて， git submodule で参照される．
  • core 開発のための最小限の user 部は Examples にあり，これを用いてビルドし，検証する．

ドキュメント

開発

セットアップ

  1. clone 後， setup.bat or setup.sh を実行

Kanban (開発マイルストーンなど)

SILS (Software-In-the-Loop-Simulation) 環境

  • C2A は， S2E などの SILS を用いて，フライトソフトウェアがそのまま実行される SILS を構築できる．
  • つまり，ターゲットの OBC 上で動くソフトウェアが， PC などの上で，そのままエミュレートできる．
  • Examples/minimum_user にある， 最小限の C2A 実行サンプルは， S2E User for C2A Core によってエミュレーション可能である．
    • また， Examples/2nd_obc_user にある 2nd OBC (非 MOBC) の user 部を使うことで， C2A 間通信も模擬できる．

テスト

  • 特定の user を仮定しないと，各種パラメタが確定しないため， Examples/minimum_user でテストする．
  • C2A 間通信に関連する部分のテストのみは Examples/2nd_obc_user を用いる．
  • 詳細は Test 参照．

ブランチ

  • main: リリース版（詳細）
  • develop: 概ね検証された最新版（beta 機能含む）
  • feature/* : 開発ブランチ
  • hotfix/* : 重大バグ修正用ブランチ

採用実績・動作実績

C2A Core の採用実績のある衛星 OBC や動作実績のあるボードの情報をまとめる．

Name Satellite    Lead Institution    Launch / Deploy CPU    Clock              ROM                     RAM                   NVRAM                 Storage                   Interface           Reference
OBC (2U) MAGNARO (Tigris) Inamori Lab. at Nagoya University 2022/10/12 STMicroelectronics STM32F4 90 MHz 2 MiB internal ROM 384 KiB internal RAM, 500 KiB external SRAM 524 KiB MRAM, 131 KiB EEPROM 16 GB SD card UART, SPI, I2C, GPIO, ADC, DCMI 1
OBC (1U) MAGNARO (Piscis) Inamori Lab. at Nagoya University 2022/10/12 STMicroelectronics STM32F4 45 MHz 2 MiB internal ROM 384 KiB internal RAM, 500 KiB external SRAM 524 KiB MRAM, 131 KiB EEPROM 16 GB SD card UART, SPI, I2C, GPIO, ADC, DCMI 1
MOBC SPHERE-1 EYE Sony Group Corporation, ISSL at the University of Tokyo 2023/01/03 Renesas Electronics SH-2A 200 MHz 2.5 MiB internal ROM 128 KiB internal RAM, 8 MiB external SRAM 2 MiB MRAM 2 GiB NAND flash memory UART (RS422, LVTTL), CCSDS (LVTTL), GPIO (LVTTL), ADC
AOBC SPHERE-1 EYE Sony Group Corporation, ISSL at the University of Tokyo 2023/01/03 Microchip Technology PIC32MX7 80 MHz 512 KiB internal ROM 128 KiB internal RAM 512 KiB FRAM None UART (RS422, RS485, LVTTL), SPI, I2C, GPIO (LVTTL), ADC
TOBC SPHERE-1 EYE Sony Group Corporation, ISSL at the University of Tokyo 2023/01/03 Microchip Technology PIC32MX7 30 MHz 512 KiB internal ROM 128 KiB internal RAM None None UART (LVTTL), I2C, GPIO (LVTTL), ADC
AOBC OPTIMAL-1 ArkEdge Space Inc. 2023/01/06
MOBC ONGLAISAT ISSL at the University of Tokyo - Renesas Electronics SH-2A 200 MHz 2.5 MiB internal ROM 128 KiB internal RAM, 8 MiB external SRAM 2 MiB MRAM 2 GiB NAND flash memory UART (RS422, LVTTL), CCSDS (LVTTL), GPIO (LVTTL), ADC 1
AOBC ONGLAISAT ISSL at the University of Tokyo - Microchip Technology PIC32MX7 80 MHz 512 KiB internal ROM 128 KiB internal RAM 512 KiB FRAM None UART (RS422, RS485, LVTTL), SPI, I2C, GPIO (LVTTL), ADC 1
TOBC ONGLAISAT ISSL at the University of Tokyo - Microchip Technology PIC32MX7 30 MHz 512 KiB internal ROM 128 KiB internal RAM None None UART (LVTTL), I2C, GPIO (LVTTL), ADC 1

関連リンク

C2A 関連ツール

User 実装例

関連 crate

協力

ArkEdge Space Inc.

質問，問い合わせ，その他なんでも

お気軽に Discussions に投稿してください．

Footnotes

  1. Ryo Suzumoto, et al. Improvement of C2A (Command-Centric Architecture) Reusability for Multiple Types of OBCs and Development of Continuous Integration Environment for Reliability of Flight Software. 33rd International Symposium on Space Technology and Science, 2022-f-58, 2022. ↩ ↩2 ↩3 ↩4 ↩5

c2a-core's People

Contributors

meltingrabbit avatar sksat avatar chutaro avatar yngyu avatar hoshika-mas avatar renovate[bot] avatar renovate-bot avatar gpioblink avatar tarotene avatar 200km avatar koba789 avatar

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