bespoke-silicon-group / bsg_sv2v Goto Github PK

Note: Assuming pure combinatorial block at ./designs/src/swerv/swerv_wrapper.sv2v.v:75 in
compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending
use of @* instead of @(...) for better match of synthesis and simulation.
./designs/src/swerv/swerv_wrapper.sv2v.v:75: ERROR: Found non-synthesizable event list!

  always @(posedge clk or N0) begin
    if(N0) begin
      dout[0] <= 1'b0;
    end else if(1'b1) begin
      dout[0] <= din[0];
    end 
  end

1. Executing Verilog-2005 frontend: ./designs/src/ariane/ariane.sv2v.v
Parsing Verilog input from `./designs/src/ariane/ariane.sv2v.v' to AST representation.
input buffer overflow, can't enlarge buffer because scanner uses REJECT

INFO: Performing wire/reg declartion optimizations.
INFO: Performing always@ reduction optimizations.
Traceback (most recent call last):
  File "/net/trenton/x/ajayi/projects/OpenROAD/alpha-release/bsg_sv2v/scripts/py/bsg_elab_to_rtl.py", line 103, in <module>
    ast_always_at_redux_opt_inplace( ast )
  File "/net/trenton/x/ajayi/projects/OpenROAD/alpha-release/bsg_sv2v/scripts/py/bsg_ast_always_at_redux_opt_inplace.py", line 82, in ast_always_at_redux_opt_inplace
    ast_always_at_redux_opt_inplace(c)
  File "/net/trenton/x/ajayi/projects/OpenROAD/alpha-release/bsg_sv2v/scripts/py/bsg_ast_always_at_redux_opt_inplace.py", line 82, in ast_always_at_redux_opt_inplace
    ast_always_at_redux_opt_inplace(c)
  File "/net/trenton/x/ajayi/projects/OpenROAD/alpha-release/bsg_sv2v/scripts/py/bsg_ast_always_at_redux_opt_inplace.py", line 53, in ast_always_at_redux_opt_inplace
    if a.sens_list == always_blocks[bot_index].sens_list:
  File "/afs/eecs.umich.edu/cadre/software/anaconda3-2018.12/lib/python3.7/site-packages/pyverilog-1.1.3-py3.7.egg/pyverilog/vparser/ast.py", line 46, in __eq__
    if c != other_children[i]: return False
IndexError: tuple index out of range

### Rename and set the real top-level design

# Check if the design name is found in the collection of designs. If not, then
# it either doesn't exist or it has been renamed (from parameters)
if { [sizeof_collection [get_designs -quiet ${DESIGN_NAME}]] == 0 } {

  set designs [get_designs -quiet -filter "@hdl_template == ${DESIGN_NAME}"]
  
  if { [sizeof_collection $designs] > 1 } {
    puts "BSG-Error: Toplevel design has multiple instances post-elaboration. This"
    puts "usually indicates that there are multiple parameterizations of the design."
    puts "This flow does not support different parameterizations of the top-level"
    puts "compile target, consider using a wrapper to uniqify the hierarchy for each"
    puts "parameter."
    exit -1
  }
  
  rename_design ${designs} ${DESIGN_NAME}
}