Produces graphical representation of HDL component. At the moment it is possible to generate SVGs out of VHDL components. A JSON configuration file represents how the output image is produced

Let's say we have the following component declaration in VHDL:

entity ExampleComp is
  port(
    io_a : in signed(3 downto 0);
    io_b : in signed(3 downto 0);
    io_c : inout signed(3 downto 0);
    io_d : out signed(31 downto 0);
    io_f : out std_logic;
    clk : in std_logic;
    reset : in std_logic
  );
end ExampleComp;

Here there are some examples of the produced images using hdltoimg:

Serif Bold font, Top Left component name, arrow style None:

Arial Bold font, Top Center component name, arrow style Full:

FreeMono Bold font, Top Right component name, arrow style Empty, standard formatting for ranged signals:

FreeSans Bold font, Bottom Left component name, arrow style Reentrant, standard formatting for ranged signals:

Serif Italic font, Bottom Right component name, arrow style Minimal, standard formatting for ranged signals:

Here it is the JSON configuration file for the last example

{
"figPadX": 4.0,
"figPadY": 4.0,
"compPadX": 1.0,
"compPadY": 2.0,
"compFont": {"font": "Times New Roman", "weight": "ITALIC", "size":11},
"compAlignment": ["Bottom", "Right"],
"boxTickness": 0.25,
"boxFillColor": [1.0, 0.5, 0.94],
"boxWidthPolicy": {"type": "BoxSigNamePad", "pad": 20.0},
"boxBorderPad": 2.0,
"sigPadX": 1.0,
"sigPadY": 1.0,
"sigFont": {"font": "Times New Roman", "weight": "ITALIC", "size":10},
"descPadX": 1.0,
"groupPadY": 10.0,
"groupPolicy": {"type": "SimplePolicy"},
"arrowLength": 30.0,
"arrowPadX": 0.0,
"arrowThickness": 1.0,
"arrowTipSize": 3.0,
"arrowStyle": "StyleMinimal",
"outputType": "SVGTypeOutput",
"removeDefaultInputArg": true,
"standardFormatting" : false
}

If HDLtoIMG is not installed system wide you can use it through sbt:

    sbt "runMain com.github.hdltoimg.vhdl.VhdlToImg -i source.vhd -c conf.json"

otherwise you can simply type

    vhdl-to-img -i source.vhd -c conf.json

Note that the the -c switch is optional. In this case a default configuration will be applied.

maps to the following JSON properties:

The resulting component box size is determined by the boxWidthPolicy field

The width of the box is constant

    "boxWidthPolicy": {"type": "BoxConstantWidth", "width": 20.0}

The width of the box is the sum of a pad value plus the size of the signal names

    "boxWidthPolicy": {"type": "BoxSigNamePad", "pad": 20.0}

The width of the box is equal to the height multiplied by a ratio

    "boxWidthPolicy": {"type": "BoxConstantRatio", "pad": 1.0}

.. for a square box

For components with a lot of ports sometimes the resulting image looks a bit difficult to read:

The above example shows the interface of a CPU. It would be better to group together the signals that belong to the same bus. This is possible using the RegexGroupsPolicy. With this policy the signals are grouped using a regex (groupRegex) that matches the group name. For example:

    "groupPolicy": {"type": "RegexGroupsPolicy", "groupRegex": "^([^_]*).*"}

Produces:

There are four options:

• PLAIN
• BOLD
• ITALIC
• BOLDITALIC

The default behaviour in the image creation process is to keep the whole signal type name as it is:

(example for as signed VHDL signal)

    signed(3 downto 0)

If the standardNotation configuration property is set, the above type is transformed to:

    signed[3:0]

• SBT
• Java JRE
• Java JDK
• zip

• dpkg-deb
• dpkg-sig
• dpkg-genchanges
• lintian
• fakeroot

• rpm
• rpm-build

• WIX Toolset

The packaging process is based on sbt-native-packager. More options for package generation are available at that site.

    sbt universal:packageBin

Generates a .zip in target/

    sbt debian:packageBin

Generates a .deb in target/

    sbt rpm:packageBin

Generates a .rpm in target/

Before launching the compilation command two values have to be adjusted in build.sbt to your Wix Toolset installation: wixProductId, wixProductUpgradeId

    sbt windows:packageBin

Generates a .msi in target/

• Cross arrows when the signal is ranged
• SpinalHDL support
• Other languages support (Verilog/Chisel)
• Test the package build process on other platforms other than Linux

All the HDL examples were produced using SpinalHDL and VexRiscv