A RTL H.265 encoder core written in Verilog. The code base is h265enc_v1.0 form http://www.openasic.org
Many thanks to Prof. Yibo Fan gave us an amazing runable H.265 encoder on FPGA!
Would like to know which low cost affordable FPGAs I can program and use this IP core?
Have any recommendations?
Also for curiosity how many logic gates are needed to run this IP core?
Thanks
Hi!
What FPGA unit did you use to run and test the Verilog codes? Because this design contains 1767 I/O ports.
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