Comments (5)
NB also that yices2 is GPLv3.
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Just noticed that license myself -- any sense for how long Bluespec has been in violation of the GPL? I assume this component wasn't added in the open source release.
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As part of making this BSC repo, to put on GitHub, I extracted code from various places and created Makefiles and cleaned things up, etc. I also decided to update the use of Yices, which predated Yices being open source (and GPLv3); so this was in fact just added, for this release. (I had also wanted to update STP, but didn't get around to it.) And, yes, it does mean that any distribution of BSC from this repo needs to respect the GPLv3 license or excise the use of Yices.
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Thanks for the clarification!
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Note that it's unclear if a newer version of Yices is needed or not for Bluespec -- without the test suite or real users of the FOSS version reporting in just yet, it's hard to know what behavioral differences there may be between now and the previous stable release. They may or may not need to do a release for us to reliably unvendor things.
That said I'm hopeful if we needed it, and someone asked them nicely, they would cut a new release. :)
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Related Issues (20)
- bluesim simulation result is different from verilog simulation, does bluesim have bug implementing UInt#(n) when n is big (eg., 72)? HOT 1
- Bluesim leaves junk in loaded registers if the full range of hex digits isn't specified HOT 3
- uppercase names not allowed in interface property `arg_names` HOT 4
- bsc ignores `always_ready` when checking for duplicate wires
- module verilog does not allow sharing ports among conflicting methods
- Improve the mechanism for testing Bluespec Inc bug 1490 HOT 3
- `-dparsed` output produces invalid register updates with BSV HOT 2
- `-dparsed` produces invalid BSV module function that takes another module as an argument HOT 2
- Missing `Ord Bool` instance HOT 7
- Static check of file descriptor argument to tasks like $fgetc HOT 3
- Testsuite reports an error getting BSC version HOT 2
- Internal Compiler Error when quoting a character value. HOT 4
- Bluesim's symbol-probing interface has wrong values for FIFO
- Unresolved numeric contexts that should be resolvable HOT 6
- Verilog import fails in macro substitution HOT 2
- Unexpected syntax error HOT 1
- expandPorts.tcl has hardcoded paths which do not exist. HOT 1
- Unexpected behavior in Stmt sequence when using par HOT 2
- Bluesim divide-by-zero behavior is inconsistent on arm64 HOT 2
- Type synonyms with phantom parameters can lead to strange behaviors (E.g., compiler hang) HOT 4
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