Bluesim divide-by-zero behavior is inconsistent on arm64 about bsc HOT 2 OPEN

I'm guessing that we probably want to have Bluesim raise SIGFPE on all architectures.

Why? That certainly does not respond to anything you'd see in hardware, right?

And it's not just ARM that doesn't trap for integer division. RISC-V returns all bits set, no trap. In PowerPC the result is undefined, no trap. The C standard leaves the result undefined.

Perhaps more relevantly, SystemVerilog defines division by 0 to result is 'x, which if you squint you could argue means undefined in some sense. But either way, no trap.

I think there are two rational things to do: either match Verilog behaviour (which we can't b/c we have no x) or leave the behaviour of things like this explicitly undefined in the language spec. I'd argue for the latter.

from bsc.

I agree with @mieszko 's suggestion to leave the behaviour of things like this explicitly undefined in the language spec.

But an intermediate point would be to wrap it in something that $displays a warning in simulation.

from bsc.