The Verilog code for 4 bit counter is shown in below

First of all the simulation is performed to test the functionality of the counter using VIVADO.

The elaborated schematic of the counter is shown below

Now the IO-planning is performed by mapping the ports of the design to baysis 3 board pins. clk port is mapped on W5 pin that is clock pin of 100MHz rst port is mapped on the R2 switch cnt[0] is mapped on U16 cnt[1] is mapped on E19 cnt[2] is mapped on U19 cnt[3] is mapped on V19

Synthesis is performed for the counter that gives the resource utilization for the counter design

Next Implementation is performed during which the design is placed and routed on the baysis 3 board architechture. After the Implementation the final timing summary is also obtained which shows a positve slack that means the design can run on 100MHz.

The last step is to generate the bitstream for baysis 3 board

For obtaining the VIO in VIVDO, the "VIO IP" instance is included in the deisgn

After that, again synthesis to bitstream generation flow is repeated that generates the bitstream to be loaded on the baysis 3 board.

To run VPR flow we need to provide synthesized netlist in the form .blif and archtecture file in .xml format as shown in following command

$VTR_ROOT/vpr/vpr
$VTR_ROOT/vtr_flow/arch/timing/EArch.xml
$VTR_ROOT/vtr_flow/benchmarks/blif/tseng.blif
--route_chan_width 100

VPR shows placement of blocks on gui

There are multiple options here in the GUI e.g. toggle nets

Toggling the block pi utilization

Critical path toggling

After clicking on the proceed VPR flow completes.

The VPR flow also performs the timing analsysis for the design.

Now we run the VTR flow, that is from HDL design.ODIN-II to VPR place&route and analysis for both timing and and power. For this we have choosen a 4bit up counter in verilog.

Run following command, it will generate several files in the directory

The important one is the pre_VPR.blif that is going to be used for further analysis using VPR flow

VPR flow running in GUI, performs the placment and routing

Post sythesis simulation is performed on the counter using VIVADO. Following command is used to generate postsyhtnesis netlist

Timing Analysis

Timing anlaysis is performed by providing the SDC contraints

• This core has several modules the main module is Core which has 3 inputs called clk, reset and output that is of 8 bits. • This adds the first 9 numbers and gives an output of 45 • The code is given here in RISCV Instructions based assembly code

• These instructions are saved in the instruction memory as binary format as shown in below figure. It is a five stage pipelined processor in which the fetch unit fetches these instructions one by one then the decode unit decodes them and the execution unit or ALU performs the execution of these instructions and access the memory and at the end write back is performed.

• Create a simple test-bench for testing the core present in the Code folder as test.v

• Now simulate the Core in VIVADO by creating a new project and selecting baysis 3 as the Board. Add the main file myth_test.v in design sources section and testbench file in sources section.

• Now perform Behavioral simulation for the design as shown in the below waveform. It shows the required output as we are expecting the sum of first 9 numbers as 45.

• Now elaborating the design. Once the elaboration is done open the IO planning and assign the W5 clock of 100MHz of Baysis 3 Board to "clk" of the core and also assign the "reset" to a switch R2. And also set the IO standar as LVCMOS33. Here I don’t assign “out” to LEDs rather I observe it on ILA.

• For observing the output on ILA I have to remove “out” port from the module definition and perform the elaboration again and now in the IO planning only the clk and reset will appear. • Before performing the synthesis we also add the timing constraints of 100 MHz using the constraint wizard in synthesis column. Below is the utilization summary of the synthesized design

• Now perform Implementation and final implemented design after place and route

• The final timing summary of the MYTH core is obtained as

SOFA(Skywater OpenSource FPGAs) consists of a series of opensource FPGA-IPs using the opensource 130nm PDK. To run the SOFA framwork its repo is clone and installed. There are multiple FPGA IPs are present in the SOFA such as:
. FPGA1212_SOFA_CHD_PNR
. FPGA1212_QLSOFA_HD_PNR
. FPGA1212_SOFA_HD_PNR
For smaller benchmark designs such as counter, here we use FPGA1212_QLSOFA_HD_PNR IP. To include the counter design first we need to add our custom four bit counter (verilog file) in FPGA1212_QLSOFA_HD_task/Bechmark directory.

Then we need to modify the "FPGA1212_QLSOFA_HD_task/config/task_simulation.conf" file as shown below:

For running the SOFA flow we need to go back to SOFA/FOGA1212_SOFA_HD_PNR/ directory and run command "make runOpenFPGA"

This will number files in the following directory

Resource utilization of counter

SDC contraints for Timing analysis

Command added used to run timing analysis for VPR flow

Run the SOFA flow again after providing the SDC file

Setup report for 4 bit counter

Hold report for 4 bit counter

Generated the post implementation netlist for functional simulation

Post implenentation netlist

Functional simulation wavform for four bit counter

Use following command in generate_testbench.openfpga

After running " make runOpenFPGA" the successful run is shown below

The VPR_stdout.log will also show the status of run

VPR provides the area results

VPR provides the detailed resource utilization of LUTs, flipflops etc. in VPR_stdout.log

VPR also provides the detail about the logic elements in VPR_stdout.log

Upon providing the sdc constraints to VPR it generates the step and hold reports for the RVMyth core. Following command is provided in the generate_testbench.openfpga for the timing analysis.

RVMyth core design is constrained by providing a period of 200ns. The sdc constraints are given below:

VPR generated the Setup report

The hold report for RVMyth generated by VPR in SOFA

The post implementation netlist is generated using VPR by provinding following command:

The post implementation netlist

A simple testbench is written to verify the RVMyth core funtionality. As it is supposed to give a sum of first 9 numbers at the output.

The simulation is performed on VIVADO by providing the primitive.v file that contains primitives used in the implementation RVMyth in SOFA. The final simulated result waveform is shown below: