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Dual Port USB Power Delivery „Charging Only“ Breakout Box Reference Design using Microchip dsPIC33CK DSC (Project-No 00173-Rev. 2.0, 05/02/2019)

C 81.35% C++ 13.54% Makefile 0.16% Assembly 3.17% Objective-C 0.13% VBA 1.64%

usb usb-host usb-c usb-pd usb-ports power-converters power-supply power-management power-electronics power-distribution-unit

usb-pd-bob's Introduction

USB-PD-BoB

Dual Port USB PD Charging Only Reference Design (Project-No 00173-Rev. 2.0, 05/02/2019)

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usb-pd-bob's Issues

Optimize Control Loops #1

Optimize ISR Time

Type: Low Level System Feature
Priority: Medium/Low

CPU load of control loops take more than 70% CPU load and result in colliding ADC triggers and control loop execution. These issues force us to step down control frequency to 87.5 kHz. Design target would be 175 kHz. This target was nice to have but 87.5 kHz might be good enough to meet PD requirements. Thus priority is lower.

Protection Features #1

Basic Protection

Type: Low System Level
Priority: Medium

Basic protection should cover UVLO, OVLO, OVP, OCP and OTP. Define and enable fault handlers for these values.

GUI Support #2

Debug UART Protocol Layer Reworks

Type: Low System Level
Priority: High

When the UART low-level driver has been exchanged against a dedicated dsPIC33C driver, the protocol layer needs to be reworked to leverage the new features and modified function calls.

GUI Support #4

PD Stack Debugging Terminal

Type: Low System Level
Priority: High

As soon as the basic GUI support is provided, PD Stack debugging information needs to be passed into the GUI terminal window. This may require a protocol layer extension supporting unlimited data frames. This transportation layer is not supported yet.

Efficiency Enhancement #1

100% On-Time Implementation

Type: Low System Level
Priority: High

Currently the PWMs are switching buck and boost legs on a cycle-by-cycle basis. As the 4-switch Buck/Boost architecture usually have either the buck-leg or boost-leg in a 100% ON condition, continuous switching results in increased losses.
The combinatorial logic of the PWM module allows selective operation of the half-bridge drives only briefly turning on the 100% half-bridge to recharge the bootstrap capacitor when needed.
Implementing this will also require to rework the PWM distribution to account for 100% on-time vs. limited PWM output.

EMC Optimizations #2

EMC Measurements

Type: Low System Level
Priority: High

EMC measurements need to be taken for presentation/documentation purposes. As soon as Spread Spectrum Modulation is implemented, comparison measurements need to be taken as well.

Optimize Control Loops #2

Stability and Performance

Type: Low System Level
Priority: Medium

Control loops are running well now but we don't know where we are. Final loop optimization can be done as soon as we get the board on the bench.

Efficiency Enhancement #2

Efficiency Measurements/Documentation

Type: Low System Level
Priority: Medium

As final step of the hardware validation and to generate data for presentations we have to run efficiency measurements under various output voltage conditions.

EMC Optimizations #1

Spread Spectrum Modulation

Type: Low System Level
Priority: High

Spread Spectrum Modulation needs to be incorporated into the PWM distribution. Implementation has been started but is on hold due to initial control loop performance limitations. As it has been decided to stay with 87.5 kHz loop frequency, the way is free to pursue the implementation.

GUI Support #3

GUI Interface Synchronization

Type: Low System Level
Priority: High

Once UART low-level driver and protocol layer have been modified, the parameters taken/provided by the code must be incorporated into the DebugUART driver of the firmware.

Protection Features #2

Enhanced Diagnostics and Protection

Type: Low System Level
Priority: Low

Enhanced protection capabilities would include plausibility checks between control loop status vs recent system status. To enable enhanced fault handling features fault objects need to be defined, configured and enabled.

GUI Support #1

UART Driver Rework

Type: Low System Level
Priority: High

The GUI is still not working with the board. The UART driver used was written for dsPIC33EP and showed a number of short-comings. Adding dsPIC33C support to the existing driver turned out to be not feasible. A new low-level UART driver has to be written and tested.

Optimize Control Loops #3

Analyzing Input Current vs. Output Current Sampling

Type: Low-System Level
Priority: Low

Currently the control system is based on output current sampling. The board still offers input current sensors, which are not used yet. A comparison between both is pending.