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responsive-resume-cv-smith

Responsive Resume Cv Website Using HTML CSS And JavaScript

responsive-sidebar-menu

Responsive Sidebar Menu

responsive-sidebar-submenu

Responsive Sidebar Menu With SubMenu HTML CSS And JavaScript

responsive-travel-website

Responsive Travel Website Design Using HTML CSS and JavaScript

responsive-web-design

All things responsive: Devices, viewports, media queries, adaptive, fluid, and how to build them.

responsive-website-restaurant

Responsive Website Restaurant Using HTML CSS And JavaScript

restaurant-vincent

restaurantmgtsampleui

A sample UI for restaurants using JavaFX

restaurants-websites

This is a simple practice with CSS

reva-university-college-uniform-detector-using-deep-learning

This project is made by Abhishek Bhandare as A mini-project for college course. This project detects whether the student is wearing college uniform or not. I have trained my dataset of REVA University college's uniform. This project is done in Jupyter notebook. I have used Keras for training the model. You can use this code to create a uniform detector for your college or any other industry

review-carousel

Ecommerce site to display customer reviews or a personal portfolio to display client reviews.

richard-ryan

Richard Ryan is a fully responsive portfolio website, Responsive for all devices, build using HTML, CSS, and JavaScript.

ridex

Ridex is fully responsive car rental website

riftcore

RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System

ripe-tomatoe-detection

rippled

Decentralized cryptocurrency blockchain daemon implementing the XRP Ledger in C++

risc-v

Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection, Branch Target Buffer using LRU replacement policy, absolute value custom instruction.

risc-v-cpu

RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.

risc-v-mpu

RISC-V based Microprocessor designed in VHDL

risc-v-processor

This is a single cycle RISC-V Processor in VHDL with ISA I32

risc-v-single-cycle-cpu

A RISC-V 32bit single-cycle CPU written in Logisim

riscv

RISC-V CPU Core (RV32IM)

riscv-asm-manual

RISC-V Assembly Programmer's Manual

riscv-buildroot-linux

riscv-core

RISC-V CPU in VHDL

riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

riscv-isa-manual

RISC-V Instruction Set Manual

riscv-multicycle

RISC-V muticycle implementation in VHDL. Core supports multiple peripherals and interruptions using a simple local interrupt controller.

riscv-pipeline

RISC-V Pipeline em VHDL.

riscv-rust

RISC-V processor emulator written in Rust+WASM