WIP open source tooling for the XC9500 / XC9500XL series of CPLDs from Xilinx.
Primary focus of efford is on the XC9572XL for now.

To get started the following documents are a good intro into the architecture:

• The Family Datasheet
• The xc3sprog code and documentation (or see submodule in bitstream/xc3sprog)

Some initial thoughts have been made on which bits / fuses exist, but they still have to be located in the bitstream.

For example bitstreams, see the misc/bitstreams/ folder.

Nothing is done on this front yet.

A complete model of the CPLD is to be written. It should be able to be "programmed" with real bitstreams in jedec format and should behave like a real cpld.

Nothing is done on this front yet.

The primary goal is to be able to go from yosys rtlil to a working bitstream in jedec file format. Timing optimization / analysis is only secondary for now.