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74xxx's Introduction

74xxx

SystemVerilog implementation for common 74xxx series ICs with testbenches

Chips implemented:

  • 3-line to 8-line decoder / demultiplexer

       Western: SN74LS138A/SN54LS138/SN54S138

       USSR: K555ID7 / К555ИД7

  • Quaduple 2 to 1 line selector/multiplexer

       Western: SN74LS257

       USSR: K555KP11/К555КП11

  • Dual 4 to 1 line selector/multiplexer

       Western: SN74LS253

       USSR: K555KP12/К555КП12

  • Quad 2 to 1 data selector / multiplexer

       Western: SN74LS157

       USSR: K555KP16 К555КП16

  • D flip-flop

       Western: SN74LS74

       USSR: K555TM2/К555ТМ2

  • Hex D-type flip-flops with clear

       Western: SN74LS172

       USSR: 555TM9/555ТМ9

  • Presettable 4-bit binary up/down counter

       Western: SN74LS193

       USSR: 555IE7 / 555ИЕ7

  • Synchronous 4-bit up/down binary counter

       Western: 74LS169

       USSR: 555IE17/555ИЕ17

  • 4 bit fully synchronous binary counter

       Western: 74LS163

       USSR: K555IE18/К555ИЕ18

74xxx's People

Contributors

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Watchers

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Forkers

tclaurentiu

74xxx's Issues

74193 behaviour not correct

Regarding the 74193 behaviour, the Verilog model does not match the datasheet:

74xxx/rtl/sn74xxxx.sv

Line 265 in 4dbb7e8

else if (up)

image
Datasheet here.

In the datasheet, CLOCK_UP and CLOCK_DOWN rest high. However, in your implementation, if DOWN is toggled while UP is high, the counter counts up instead of down due to the else-if priority ordering.

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