Comments (1)
Those were basically proof of concept modules. After writing those, I realized that rolling the FCS code, length enforcement, and interface conversion made more sense than using separate modules. There is no need to use those modules unless you're trying to do something weird.
from verilog-ethernet.
Related Issues (20)
- I want to send custom data, how should I modify the program?
- Question about the project coding style
- Question - Verilog-Ethernet vs 1G/2.5G Ethernet Subsystem HOT 2
- Difficulties in putting the DE2-115 example into operation
- NetFPGA_SUME for kintex ultrascale HOT 2
- There is no data return in ZCU106 example design HOT 2
- PHY MAC latency HOT 1
- Bug in ssio_sdr_in_diff.v
- Can this IP support 100G Ethernet? HOT 1
- Does this 10G ethernet library use pause frames for flow control? HOT 4
- Misalignment/Deadlock in udp_checksum_gen_64.v
- VCU 128 Support! HOT 3
- ExaNIC_X10 HOT 4
- UDP flow
- UDP flow HOT 1
- How To Trigger ARP Mechanism? HOT 2
- Can this design be validated on Alveo u50 card ? HOT 9
- How to simulate and test the verilog-ethernet design? HOT 6
- Unreachable code in ip_eth_tx_64.v HOT 1
- Is there a block diagram available for the UDP echo server design ?
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from verilog-ethernet.