Comments (2)
Have you tried arping and looking in Wireshark?
from verilog-ethernet.
I have tried arping and looking in Wireshark,after i use the' hping3 192.168.1.128 -2 -p 1234 -d 1024 command ', i can see the arp request was sent in wireshark ,but i can't capture the arp pakcet in vivado (i use ila to capture the axis interface between phy layer and mac layer) ,and so there is no arp reply in wireshark . I also tried to using the 10g/25g Ethernet Subsysterm instead of the phy layer in the example design of zcu106. This time ,i can capture the arp request packet in vivado, but still no arp reply packet was send by the fpga.figure1 is hte arp request packet i capture in vivado,
As conclusion ,after i using the 10g/25g Ethernet subsysterm i can receive the arp request packet but no arp reply packet was send.As a result, there are still problems
from verilog-ethernet.
Related Issues (20)
- PHY MAC latency HOT 1
- Bug in ssio_sdr_in_diff.v
- Can this IP support 100G Ethernet? HOT 1
- Does this 10G ethernet library use pause frames for flow control? HOT 4
- Misalignment/Deadlock in udp_checksum_gen_64.v
- VCU 128 Support! HOT 3
- ExaNIC_X10 HOT 4
- UDP flow
- UDP flow HOT 1
- How To Trigger ARP Mechanism? HOT 2
- Can this design be validated on Alveo u50 card ? HOT 9
- How to simulate and test the verilog-ethernet design? HOT 6
- Unreachable code in ip_eth_tx_64.v HOT 1
- Is there a block diagram available for the UDP echo server design ?
- How to download and install Icarus Verilog in linux environment? HOT 1
- `test_ip_eth_tx_64.py` hangs HOT 4
- Jumbo Frame Support - Not Working HOT 2
- SGMII design in Stratix 10 using Gx bank HOT 6
- Bug in udp_checksum_gen
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from verilog-ethernet.