Comments (2)
alexforencich
commented on May 18, 2024
The example designs connect PHYs to all of the GTY channels, but only one of them is connected to the MAC and the rest of the design.
How are you testing the data rate?
from verilog-ethernet.
alexforencich
commented on May 18, 2024
I just found the issue; the register type was set incorrectly on the AXI stream switch that is used for inserting the gigabit port into the high speed path on the VCU108 and VCU118 designs. The reg type that was selected was a non-skid-buffer, which uses one set of registers but has a throughput of half. The correct reg type is a full skid buffer that provides full throughput.
from verilog-ethernet.
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from verilog-ethernet.