Comments (2)
alexforencich
commented on May 18, 2024
Whoops; should be fixed now.
from verilog-ethernet.
CodeWarrior1241
commented on May 18, 2024
Hi Alex,
I'm now porting your UDP core to the ZC706 board. Is this worth
contributing back to you?
I'm using Vivado 2015.4. For the MAC/PHY I'm using the Ethernet Subsystem
3.0, which combines the transceiver wizard, PCS/PMA core, and the 10GBASE-R
MAC core.
This isn't something you already have, right? It's not wasted effort?
On Fri, Feb 12, 2016 at 9:30 PM, Alex Forencich [email protected]
wrote:
—
Reply to this email directly or view it on GitHub
#2 (comment)
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from verilog-ethernet.
Related Issues (20)
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