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blinkencard's Issues

Keep vias away from silk

Insure that vias stay clear of any silk on the 'front panel' back silk layer. Vias break up silkscreen, and can make the fine text on the front panel illegible. Seems to be done mostly well with V2.0, but back silk layer needs more thorough review for future revs.

The only violations of this are around the 'STATUS' legend under the status LED bank. This is an issue on both v1.0 and v2.0 PCBs.

v2.0 - Increase silk text and line width on the front panel

JLCPCB does a reasonable job of printing silk, but their process does not seem consistent from run to run as evidenced by minor gaps in some lines in v2.0 vs v1.0. Increase the line width for graphics and text to avoid this in the future.

v2.0 BOM errors

  • C1, C2 0.01uF cap is 0805, should be 0603
  • D2 green SMD LED is R/A, but footprint is not. R/A facing outward is correct, should change footprint to match.

Cp2102N is too slow to bitbang the SPI flash

Programming the 8MByte flash with the CP2102N would take over a day at the ~2kHz SCK rate that flashrom generates.

The only clear solution is to move to a FT232H or FT2232H in the next rev

Reduce gnd via diameter

The large ground vias are too visible on the display side of the board. Replace with smaller vias, and double up if necessary.

Rotate the battery connector 180 degrees

With the battery connector oriented the way it is, the leads from the battery drape over the ESP32 module antenna. Rotate the connector so this doesn't happen.

Packages for QFNs did not solder properly

In v1.0, the footprints for the CP2102N and FPGA seemed to have too much paste at the center, preventing the pins from soldering properly.

Fix by using packages without via slugs and with smaller paste apertures for the slugs. Or be more careful applying paste next time.

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