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karaoke-tone-control-circuit's Introduction

๐Ÿ‘‹ Hi there! I'm Ahan Malli

I'm a soon-to-be graduate in Computer Engineering from The Pennsylvania State University, with a minor in Cybersecurity Computational Foundations. I am passionate about software development, cloud computing, and computer architecture. I have interned at Amazon Web Services and have practical experience in developing scalable and efficient software solutions.


๐Ÿ›  Skills

  • Programming Languages: Python, Java, C, C++, SQL, TypeScript, HTML, CSS, Verilog, MIPS Assembly (RISC), Bash
  • Frameworks and Libraries: Android, JDBC, Scikit-learn, Keras, TensorFlow, Apache Spark, JSoup, PyTorch, JavaFX
  • Cloud Services: AWS (Kinesis, Glue, CDK, DynamoDB, Lambda, S3, SDK), Terraform
  • Tools and Tech: GIT, OOP, ML, Basic Deep Learning, CI/CD, Agile, Unix/Linux, IaC, Docker, Computer Networking

๐ŸŒฑ Iโ€™m currently learning

  • Typescript and Java for developing a Figma-like GUI for AWS Cloud Development Kit
  • Advanced networking and cloud architecture
  • Deepening my knowledge in Machine Learning and Data Science

๐Ÿ’ผ Experience

  • Software Development Engineer Intern at AWS: Worked on transitioning an internal data ingestion service from batch processing to real-time streaming, reducing latency by 3600%. More details
  • Software Engineer Intern at Han Digital Solution: Developed a LinkedIn tracking platform for recruiters, increasing recruiter message responses by 150%. More details
  • Software Developer Intern at Let's Service Automotive Technologies: Created a native Android app to locate public restrooms in Bangalore. More details

๐Ÿ”ญ Projects

  • AWS Infrastructure as Code GUI: A graphical user interface for AWS CDK to make Infrastructure as Code more accessible. More details
  • Thread Scheduler Implementation: A scheduler for managing threads with various CPU and IO operations. More details
  • Unix Virtual Memory Management System: A two-level page table for virtual memory with TLB emulation. More details
  • 5-Stage MIPS Pipelined CPU: A RISC 5-staged 32-bit MIPS pipelined CPU implemented in Verilog. More details
  • And many more on my GitHub repositories!

๐Ÿ“ซ How to reach me:


Feel free to check out my projects and don't hesitate to reach out if you have any questions or just want to connect!

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