- Quartus Prime Lite Edition v20.1
- Install wls1 with Ubuntu 18.04
- Install Quartus Prime Lite Edition v20.1 with device support for Cyclone IV
- Procceed with instruction taken from section 3.1 of the Nios II hanbook
All oh the instruction about creation of the project could be taken from here with relate to platform specifics like memory size or UART-JTAG from here
Use this instruction of how to generate ip-core
In a nutshell, use command
setupAXIMasterForQuartus('path')
It's has to be mentioned that Altera Interconnection Bus is Avalon, which could be different from AXI interface. But Platform Designer is still able to correctly recognize and solve component interconnections
Don't forget that Matlab generated IP core is not a standart one, so you have to look for it in a project-specific ip-core in Platform Designer
Here is a complite guide of matlab-jtag-fpga interaction. Use memory addresses which you previously assigned in Platform Designer in Address Map tab.