This project forked from jmkmay/adsd-project
Verilog code and jpg files for a Type II IIR Filter
Verilog code and jpg files for a Type II IIR Filter
Jonathan May UBC Okanagan
Input is given as a text file which each line corresponding to an audio input in binary. Output is given as a text file where each line is the corresponding output of the input file being passed through the filter.
Output file is taken into MATLAB and converted from binary into decimal. MATLAB is used to plot input/output relationship to visualize the effects of the filter.
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