zli87's Projects
Simulator for Coherence protocol, parallel programming acceleration with OpenMP, MPI, Hybrid
https://caravel-user-project.readthedocs.io
This resource comes from UCSD’s 237C Parallel Programming for FPGAs. Currently, try to finish this tutorial through vitis_hls 2020.
Integrated Circuit Design Laboratory(IC Lab) at 2019 Fall, NCTU. Final project is a customized 16 bits ISA processor.
Markdown - you can mark up titles, lists, tables, etc., in a much cleaner, readable and accurate way if you do it with HTML.
Cache_Simulator, Branch_Prediction and Dynamic_Instruction_Scheduling
my testing project
Implement process scheduling, lock with priority inheritance, demand paging in XINU OS. All projects pass all tests
MIPS Processor, BNN Accelerator, AXI4 interface, Cache Controller and LRU replacement
These are some coursework related to SystemVerilog Design & Verification in a graduate-level course, Integrated_Circuit_Design_Laboratory_IC_Lab, at NCTU.
This repo shows my practice of some interview questions.
ASIC Verification at 2022 Spring. This course only use SystemVerilog, did not use UVM.
Config files for my GitHub profile.