TopLevel_quick.t.v TopLevel_full.t.v

gtkwave dspTopLevel.vcd

you can also use the make file by running $make

to make a new .dat file from an .asm use $ python assembler.py /path/to/test_file.asm`

For this project, we plan on delving into digital signal processing and its relation to computer architecture. In particular, we want to explore architectural solutions and implementations. We will start off trying to become well versed in the topic, understanding the current use of DSP. Then the focus is to shift to understanding of the architecture. Some modules of interest include multiplier, MAC, filter, and memory. We will scale up from understanding, to designing, and then implementing. We will focus on modules like the (ALU), multiply-accumulator (MAC), barrel-shifter, and memory busses­ and numeric operations of DSP. We imagine that we will end this project with a design and several of these core modules implemented in verilog.

Success for us is fully understanding what we are implementing. We are striving to implement as many modules as we can, but we want to understand the datapath and architecture we choose more than we want to present a fully functioning DSP unit.

Lecture on DSP architecture from Berkeley

Analog Devices’ Beginners guide to Digital Signal Processing

Minimum: Teach class about DSP and its relation to CompArch

Planned: Teach class and design DSP architecture

Stretch: Implement DSP architecture in Verilog