- š Hi, Iām @zeeshandildar
- š Iām interested in RISCV based designs and their verification
- š± Iām currently learning UVM for verification
- šļø Iām looking to collaborate on any project related to verification of RISCV based Core and Peripheral IPs
- š« How to reach me [email protected]
zeeshandildar Goto Github PK
Name: Zeeshan Dildar
Type: User
Company: @bsc_cns
Bio: Verification Engineer RISC-V | Design Verification | SoCs | Computer Architecture | Vector Processing Unit
Location: Barcelona, Spain