Comments (6)
We also agree that moving the focus of your QA process to sv-tests is a worthy idea. However, to get the most out of it, the sv-tests would need to be divided into two sub-categories:
- for RTL and Synth
- for Sim and DV, perhaps even with UVM sub-sub-category
or provide a mechanism for marking selected SV features (along with tests that validate them) as NA. Those should then show greyed out and not contribute to your total score. We assume that all that the sv2v cares about at the moment is the RTL/Synth subset of the language.
sv-tests provides some value to me even though it complains about features that are out of scope for sv2v. I know these features are out of scope and can focus my efforts elsewhere. Certainly it would be great for sv-tests to incorporate your suggestions to improve its signal to noise ratio, but I don't have the bandwidth to take on that project.
In the meantime, the life goes on, and your private library of test designs may need to grow with it 😉...
I wouldn't call the tests private! They're all committed into the repo. I'm happy for contributors to add more test coverage in line with the guidelines (https://github.com/zachjs/sv2v/blob/master/test/README.md). Indeed, some of the tests come directly from outside contributors or are based on test cases provided in bug reports. If you find a bug in sv2v, please report that bug!
from sv2v.
@chili-chips-ba That is how sv-tests currently works for Yosys and Synlig: chipsalliance/sv-tests#5139. The functionality can be easily extended to sv2v
from sv2v.
Although sv2v has extensive test coverage (you can check its code coverage with make coverage
), this repository doesn't include regression tests, per se. sv-tests already covers a handful of large open source SystemVerilog projects. My gut feeling is that it would be best for the community to focus our regression testing efforts into the sv-tests project. What do you think?
from sv2v.
While we are not sure about the internal workings of sv2v QA process, we were under the impression that you were taking only occasional and cursory look at sv-tests
"... indeed sv2v has hundreds of its own tests, generally focusing on just a few features at a time. I do use the sv-tests dashboard from time to time to check in on its assessment of sv2v..."
We also agree that moving the focus of your QA process to sv-tests is a worthy idea. However, to get the most out of it, the sv-tests would need to be divided into two sub-categories:
- for RTL and Synth
- for Sim and DV, perhaps even with UVM sub-sub-category
or provide a mechanism for marking selected SV features (along with tests that validate them) as NA. Those should then show greyed out and not contribute to your total score. We assume that all that the sv2v cares about at the moment is the RTL/Synth subset of the language.
In the meantime, the life goes on, and your private library of test designs may need to grow with it 😉...
from sv2v.
@hzeller anything you can do about dividing sv-tests into two sub-categories (1) RTL/Synth; (2) DV/Sim, possibly with UVM as a sub-sub-category?!
from sv2v.
Thank you for starting this discussion! I don't think there are outstanding action items for sv2v, as sv-tests is better suited for these sorts of large and widely-applicable test cases. I am closing this issue.
from sv2v.
Related Issues (20)
- SV2V automatically removes parentheses in operator precedence HOT 6
- Option to Convert Procedural Blocks to Modules
- Support for `unique` and `priority`
- Mutidimensional Packed Arrays Handler Does Not Match Commercial Synthesis Tools HOT 1
- Token '#' issue in wire definition and assignment HOT 1
- Convert severity tasks to Verilog HOT 3
- Automatic Function Produces Construct with Infinite Loop in Yosys HOT 4
- LLVM dependency HOT 4
- Add support for `disable` statement HOT 4
- File name too long HOT 3
- regarding system verilog to verilog HOT 8
- How to build on GNU/Linux on ppc64? HOT 9
- How to build on GNU/Linux on arm64? HOT 16
- Build fails on MacOS HOT 2
- Integration with SVase?! HOT 6
- Non-exhaustive patterns in Part _ _ Module _ name _ _ with --write=DIR option HOT 5
- [Feature Request] Copy comments over HOT 4
- Assert Property ```disable iff``` not fully converted to Verilog HOT 2
- Missing "wire" keyword HOT 2
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