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efinix

heterosim

HeteroSim is a full system simulator supporting x86 multicore processors combined with a FPGA via bus-based architecture. Flexible design space exploration is enabled by a wide range of system configurations. A complete simulation flow with compiler support is provided so that a full system simulation can be performed with various performance metrics returned.

hls_recurse

Recursion for High Level Synthesis

hw

RTL, Cmodel, and testbench for NVDLA

i2s

i2s core, with support for both transmit and receive

ice40_audio

verilog example to drive PCM5102 DAC with FPGA

legup

Logic Engine for Grid-Using Puzzles - a better way to learn formal logic

legup-tuner

Autotuning High-Level Synthesis for FPGAs

squeezedet

A tensorflow implementation for SqueezeDet, a convolutional neural network for object detection.

tflite_zynq

Example code and instructions on getting Tensorflow Lite running on a Xilinx Zynq

verilog-i2s-transciever

I2S transciever implemented in Verilog HDL

video_systems

Video compression systems