QVGA enhancement request about timetoexplore HOT 4 CLOSED

Peepo,

Thank you for your message. You've not said what FPGA you're using so it's hard to be specific, but I'll do my best to help.

Buffering Row
You can use ram to buffer rows of pixels as required. The dimensions of your buffer depend on the bit depth of the data, for example if you have a row of 320 x 8-bit pixels you need something like: reg [7:0] line_buffer [0:319]. This will use logic gates to create ram in Vivado; if you want to use block ram (see clock domain answer, below) then see the sram module in https://timetoexplore.net/blog/arty-fpga-vga-verilog-03

Pixel Doubling on Rows and Duplicating Rows
I'm guessing you're trying to scale 320x240 to 640x480 for display? Rather than scale your data up, you can adjust the co-ordinates generated by the vga640x480 module.

For example, to turn 640x480 into 320x240 use a right shift to divide by two:

wire [7:0] o_x_qvga = o_x >> 1;
wire [8:0] o_y_qvga = o_y >> 1;

That way every pixel of camera data will be shown on two pixels on the display.
To repeat a line use a buffering row as you've mentioned.

Horizontal Sync Fix
I'm not sure what you mean by this. Are you trying to match horizontal sync of the display to the camera?

Clock Domain Crossing
Clock domain crossing is a big and complex topic. However, you may be able to avoid the issue by using dual-port block ram (BRAM). For example, you can have your camera data written to port A at frequency X and the display controller read data from port B at frequency Y. If you're using Xilinx FPGAs then you can find a dual-port block ram template in Vivado.

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Will,

thanks for the prompt response,

as you suggest: I am trying to scale 320x240 to 640x480 for display,
and I cannot find an example anywhere...

I am still confused, after further consideration I think I forgot to include the requirement:
the end or start of blanking keeps the display in sync with camera,
and the display uses a counter to create its hsync and vsync
is that correct?

a working example would be great!

ie the input is say 6.28 mhz and display is 25.12mhz
and as I understand it the hsync will be timed differently,
ie ~262/frame from the camera and 525 to the display.

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Peepo,

I'm afraid this isn't something I can quickly rustle up a example for you.
Good luck with your project.

Will

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appreciated!

does seem extraordinary that binning is universal,
and its complement not found....

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