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I am a M.S.E student in the Shenzhen Institute for Advanced Study at University of Electronic Science and Technology of China, supervised by Xili Han. I received my B.E degree from college of Electronic Engineering, South China Agricultural University. I used to intern at Guangdong Institute of Intelligence Science and Technology, GDIIST.

👯 I'll be graduating in June 2025, and am actively looking for the Ph.D program.

🔭 Expertise

• Proficient in Verilog, SystemVerilog and UVM, experience in joint debugging of hardware and software;
• Proficient in using Xilinx FPGAs, familiar with digital logic design (including module design, RTL programming, simulation and verification, etc.);
• Familiar with programming language such as C++ and Python;
• Experience in FPGA prototype verification and ASIC to FPGA engineering conversion;