Comments (4)
See #27 and #31 before fixing this issue.
from vicuna.
@stevobailey Thanks, I was not aware that this was a problem with certain tools. Thanks also for your patches!
I am currently in talks with the OpenHW Group who might be interested in evaluating Vicuna in an industrial context. However, they require that Vicuna switches to an Apache-based license (most likely the Solderpad HW license) instead of the current MIT-based ISC license for that.
If that is fine with you, I would merge your pull requests after updating the license (which probably will happen this week). Please let me know if there are any issues with your patches being contributed under a new Apache-based license.
from vicuna.
That's really cool!
My contributions can be under either license.
from vicuna.
Thanks a lot! I have switched to the Solderpad HW license v2.1 and merged your pull requests.
I will add the instruction ID width as a parameter to vproc_core.sv
to close this issue as well.
from vicuna.
Related Issues (20)
- Vicuna accepts instructions for which source registers are not valid.
- Wrong result generated by multiply unit (probably control logic related) HOT 1
- Wrong operand for `vwmacc(u|us|su).vx`
- narrowing instructions are never popped from the instruction queue HOT 1
- Vicuna + Ibex and WFI
- No way to clear a cache error?
- fail to set VREG_W=2048 HOT 2
- Floating point support.
- Combinatorial Loop Alert while Generating bitstream for vicuna using CV32E40X as a scalar core
- 'Illegal Instruction' when executing sign and zero extend functions when destination LMUL=8
- Error in Questasim Simulation
- Reserved word not implemented: 'config' HOT 1
- Machine mode CSRs not accessible with Ibex host core when using Vicuna's verilated model HOT 1
- Certain applications when executed with dual and triple pipeline configurations on verilated model of Vicuna hang indefinittely
- Applications hang indefinitely on Verilator when size of data cache is different than 0 HOT 1
- Suggestion for vectorizing MaxPool and Convolution Layer HOT 1
- Rounding issue for `vasub(u).(vv|vx)`
- Tail-undisturbed policy violation for comparison instructions.
- Masking not working
- `vslidedown.(vx|vi)` issue when VLMAX is exceeded
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from vicuna.