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Name: Vano Mazashvili
Type: User
Bio: Student at Sapienza University of Rome
Location: Tbilisi, Georgia
Name: Vano Mazashvili
Type: User
Bio: Student at Sapienza University of Rome
Location: Tbilisi, Georgia
I made this project while taking ASP.NET Core 3.1 course on freecodecamp.org
FSM written in Verilog. Calculates GCD for two signed 32 bit numbers.
ASP.NET Core C# and Nuxtjs project
Completed the decoder unit of the simple CPU, and added the datapath control logics
simple Mealy FSM done in verilog for Altera Cylcone V GX Starter kit. the code is written using three always statements. verilog file containing code with two always block is also included
Masktune Project reimplementation
parallel to serial/ serial to parallel shift register in Verilog
Program Counter module. In adders, instead of +4 for byte addressing, use +1 (word addressing)
seven segment display controller
Shift register with a depth of 3 programmed in Verilog on Altera V GX Starter Kit.
Verilog UART
Vision and Perception project for 2021/2022 academic year at Sapienza University of Rome
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JavaScript (JS) is a lightweight interpreted programming language with first-class functions.
Some thing interesting about web. New door for the world.
A server is a program made to process requests and deliver data to clients.
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Some thing interesting about visualization, use data art
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Open source projects and samples from Microsoft.
Google ❤️ Open Source for everyone.
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Data-Driven Documents codes.
China tencent open source team.