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cv32e40px

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

cv32e40x

4 stage, in-order, compute RISC-V core based on the CV32E40P

keccak_integration

len5

LEN5 is a coonfigurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.

loki

marlin

MARLIN: a Co-design Methodology for Approximate ReconfigurabLe Inference of Neural Networks at the Edge

ntt_intt_kyber

pulp-runtime

Simple runtime for Pulp platforms

pulp_soc

pulp_soc is the core building component of PULP based SoCs

pulpissimo

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

trng

x-heep

eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V