verilognexus Goto Github PK
Type: Organization
verilognexus's Projects
32-verilog-mini-projects
Implementing 32 Verilog Mini Projects.
4096bit-iddmm-verilog
4096bit Iterative digit-digit Montgomery Multiplication in Verilog
aes-sboxes
Somewhere to put different implementations of the AES SBox
async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
basic_verilog
Must-have verilog systemverilog modules
cmos2gram2vga
ov7670->sdram->vga
core_jpeg
High throughput JPEG decoder in Verilog for FPGA
dbgbus
A collection of debugging busses developed and presented at zipcpu.com
delta-sigma-adc-verilog
Delta-sigma ADC,PDM audio FPGA Implementation
delta-sigma-dac-verilog
Delta Sigma DAC FPGA
des_verilog
DES verilog
fmcw_radar
FMCW Radar verilog project
i2c_edid
I2C ROM for EDID (Extended Display Identification Data) on FPGAs
jt12
FM sound source written in Verilog, fully compatible with YM2612, YM3438 (JT12), YM2203 (JT03) and YM2610 (JT10)
open5g_phy
A ressource efficient, customizable, synthesizable 5G NR lower PHY written in Verilog
ov_camera_on_fpga
OV7670 (Verilog HDL)Drive for FPGA
sdram-controller
Verilog SDRAM memory controller
sdram_core
A simple SDRAM controller in page burst mode
sdspi
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
slang
SystemVerilog compiler and language services
surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
sv-parser
SystemVerilog parser library fully compliant with IEEE 1800-2017
sv-tests
Test suite designed to check compliance with the SystemVerilog standard.
sv2v
SystemVerilog to Verilog conversion
synlig
SystemVerilog support for Yosys
uart-simple
A simple implementation of a UART modem in Verilog.
uberddr3
Opensource DDR3 Controller
usb-pd-3.1-verilog
USB-PD-3.1-Verilog
usb-pd-verilog
USB Type-C Power Delivery FPGA
usbcorev
A full-speed device-side USB peripheral core written in Verilog.
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