Lits not being marked as lits + LUTs about dsptools HOT 6 OPEN

@chick @grebe do you have opinions on how to deal with this?

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Ok, I fixed the problem for DspReal and DspComplex. Now their components show up as Lits if they're meant to be Lits.

For Vec, I guess, b/c it's supposed to be dynamically addressable, you wouldn't consider its constituents Lit's anymore. Which is weird b/c that logic is inconsistent with the Verilog that's printed out... Dynamically addressable stuff that's not considered a Lit should be implemented more like the stuff in the pdf.

Otherwise, it makes no difference to use Seq or IndexedSeq instead for a LUT?

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I believe this is related to chipsalliance/chisel3#418 and to an extent chipsalliance/chisel3#417. @ducky64 talked about it at the recent chisel meeting. It's not at all clear to me what the right thing to do is, especially with Vecs (which I think are inconsistent in dealing with literals). @ducky64, can you chime in?

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There's currently no resolution to those issues (and we didn't get around to discussing those at the last meeting). If you can come up with a consistent solution, that would be great. But I think it's a hard problem.

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I think the best way to go about it is:
Vec of all Lits -> ROM (!)
Where the ROM output looks more like example 5.10 in http://www.csee.umbc.edu/%7Etinoosh/cmpe415/slides/Rom-LUT-verilog.pdf
If you construct it like that, then it matches with the behavior of doing lut(0).isLit reporting false and therefore having peek/poke tester crap out. :D

For the DspReal and DspComplex cases, I'd argue that they just weren't designed to be super compatible with the intention of Chisel UInt, etc. Lits... but that's fixed in my PR.

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The main problem (as per the linked issues) is that it's not possible given the current structure to statically resolve whether a Data is a literal. cloneType makes this especially difficult since it returns this.type, whereas you want ULit.cloneType (for example) to return a UInt.

It would seem reasonable for a Vec of Lits to generate a ROM, perhaps as a FIRRTL pass? @azidar ?

Your link also gives me a forbidden error...

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