Comments (1)
Interesting.
To clarify the use case a bit: this is mainly meant to help with waveform viewer startup cost? As in, once you get the waveform viewer started and configure the view to your liking (including adding signals), there would be very little difference between the automated proposal and your current manual workflow?
On one hand, I think there's definitely utility in making waveforms as easy as possible (one antipattern I see with novices is the tendency to debug by trial and error rather than starting up tools that give debug data and system visibility, likely because of the high perceived cost), but on the other hand, it's potentially a lot of engineering to eliminate a somewhat small startup cost (or maybe it's not as small as I'm interpreting it to be?).
That aside, I think there's a few practical details to resolve:
- Where should the start-waveform-viewer flag be put?
- Since the primary use case I see for chiseltest is regressions, writing it in the test case seems a bit unclean. Practically, it could be something sprinkled in during the debug phase, then removed once things are fixed. But it still feels weird...
- Alternatively, it might make more sense to be done automatically(-ish) on a test failure, with the expectation that this is where you want to see the waveform. The devil's in the details, though, since this would balance discoverability with not being too annoying.
- This could also be an annotation or integrated into however we do options.
- Should it be written inline with the test (and should the positioning of this construct within the rest of the test sequence be meaningful), or as something to be done on a completed test? (and presumably, the completed test would have needed VCD dumping turned on)
- Is there universal (or at least widespread) agreement on what the default view should be? For example, it probably makes sense to display top-level IO by default, but I could see arguments for and against internal wires or internal module IOs.
- How would this (or would this even) support multiple tests that have the
.viewWaveform()
? - There would probably need to be some abstraction layer to support other viewers in the future.
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Related Issues (20)
- JRE detects `EXCEPTION_ACCESS_VIOLATION` when trying to use Verilator as Chiseltest's backend HOT 2
- Report assert message with `FailedBoundedCheckException` HOT 1
- Generate waveform file in real-time HOT 1
- chiseltest gets the signal name wrong when trying to peek, poke, or expect an OpaqueType HOT 3
- Solver Chosen Constants for Formal Verification HOT 3
- scala.NotImplementedError: TODO: convert ThrowOnFirstErrorAnnotation HOT 3
- Bundle literal construction outside test() is not allowed in Chiseltest 5.0.0 (works in 0.5.4) HOT 2
- assertion failed: The Chisel compiler plugin is now required for compiling Chisel code HOT 1
- The waveform doesn't reflect changes in the input port until io.clock.peek HOT 1
- scala.NotImplementedError: TODO: convert DecodeTableAnnotatio HOT 7
- Will there be a chiseltest 6.0.0? HOT 16
- Frequent crash on macOS with the threaded Verilator backend HOT 6
- AXI4RAM test failed on chiseltest 5.0.2 HOT 2
- Cant ```import chiseltest._``` HOT 1
- Bitwuzla has changed it's command line argument format HOT 1
- [WARNING] Unsupported annotation: SRAMAnnotation
- [Help]A TLRAM test failed log HOT 8
- What are the future use cases of ChiselTest if it is replaced by ChiselSim? HOT 4
- Who is the copyright holder of chiseltest and what is the license? HOT 1
- one step takes extremely long time to complete HOT 2
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