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sdtwigg avatar sdtwigg commented on August 15, 2024
package Top

import Chisel._
import Node._

class SeqMem[T <: Data](depth: Int)(data: T) extends Component {
    val addr_width = log2Up(depth)

    override val io = new Bundle {
        val write = new Bundle {
            val valid = Bool(INPUT)
            val address = UFix(INPUT, width=addr_width)
            val payload = data.clone.asInput
        }

        val read = new Bundle {
            val address  = UFix(INPUT, width=addr_width)
            val response = data.clone.asOutput 
        }
    }

    val memory = Mem(depth, true){data.clone}

    // Write port
    when ( io.write.valid ) { memory(io.write.address) := io.write.payload}

    // Read port
    val reg_raddr = Reg() {UFix(width=addr_width)}
    reg_raddr := io.read.address
    io.read.response := memory(reg_raddr)
}
object SeqMem { def apply[T <: Data](depth: Int)(data: T) = new SeqMem(depth)(data) }

class TestType extends Bundle {
    val a = Bits(width=7)
    val b = Fix(width=8)
    val c = Bool()
}

object top_main {
    def main(args: Array[String]): Unit = {
        chiselMain(args, () => new SeqMem(16)(new TestType))
    }
}

from chisel2-deprecated.

aswaterman avatar aswaterman commented on August 15, 2024

This has since been resolved.

from chisel2-deprecated.

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