Related Issues (20)
- Documentation rendering issue HOT 7
- What is the correct way to update the mirrored state of a register? HOT 7
- Bug in uvm_reg_map.py HOT 3
- Typo in uvm_reg_field.py HOT 2
- Correct way to clean up UVM objects HOT 2
- Latest version of cocotb Verilator will always issue error %Error-TIMESCALEMOD. HOT 4
- test uvm-python/test/examples/integrated/ubus/examples for "read modify write" can not be randomized with the uvm_do_with HOT 3
- Cross TLM communication HOT 2
- uvm hw reset sequence bug HOT 2
- Test failing HOT 1
- uvm_do doesn't work HOT 2
- Using uvm-python for with custom build infrastructure HOT 4
- Is there a way to mix SystemVerilog UVM and UVM-Python environments? HOT 2
- Should we use PyVSC with UVM-Python to get constrained random and coverage working? Or, is there something similar already in the library? HOT 1
- Any example that shows integrating C++/SystemC predictor? HOT 1
- examples/sv is failing ... any ideas? HOT 1
- Do you support uvm_component_param_utils? Any alternative approach? Any example? HOT 3
- how should I use the force function in the UVM-Python verification environment, or is there a similar function to force in UVM-Python? HOT 2
- It seems there are some problems in starting the sequence by using the way of UVMConfigDb.set(self, "xxx.xxx_vsqr.main_phase", "default_sequence", self.vseq ). HOT 3
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