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accdnn

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

accelerating-cnn-with-fpga

This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.

awesome-federated-learning

Federated Learning Library: https://fedml.ai

cnn-fpga

使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用

cnn-fpga-1

cnn-on-fpga

FPGA

cnn_for_slr

A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.

cnn_hardware_acclerator_for_fpga

This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs

communication-matlab

对通信原理的内容的matlab实现

convolution_network_on_fpga

CNN acceleration on virtex-7 FPGA with verilog HDL

conways-game-of-life

A Verilog implementation of Conway's Game of Life

deeplearning-tensorflow2

本专栏我将使用谷歌TensorFlow2.0框架逐一复现经典的卷积神经网络：LeNet、AlexNet、VGG系列、GooLeNet、ResNet 系列、DenseNet 系列，以及现在比较流行的：RCNN系列、SSD、YOLO系列等。

dfl-pens

Decentralized federated learning of deep neural networks on non-iid data

dw2tf

Darknet Weights to TensorFlow

hls-lenet

The CNN based on the Xilinx Vivado HLS

image-classification-using-cnn-on-fpga

Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.

keras-yolo3

A Keras implementation of YOLOv3 (Tensorflow backend)

mnist-nnet-hls-zynq7020-fpga

to illustrate how to removal a Neural Network from pc to FPGA board ,it contain all the code include c code worked in pc,HLS prj accelerate code in FPGA,and implacement in block design and with SDK app......

must-reading-on-isac

Must Reading Papers, Research Library, Open-Source Code on Integrated Sensing and Communications (aka. Joint Radar and Communications, Joint Sensing and Communications)

netron

Visualizer for neural network, deep learning, and machine learning models

tiny_yolo_v3_zynq

Implement Tiny YOLO v3 on ZYNQ

ultra96-yolov4-tiny-and-yolo-fastest

Yolov4-tiny and Yolo-Fastest (Tensorflow2) is used to detect vehicles on Ultra96-v2 board, and we support model pruning.

verilog-generator-of-neural-net-digit-detector-for-fpga

Verilog Generator of Neural Net Digit Detector for FPGA

xfopencv

yolo-fastest

:zap: Yolo universal target detection model combined with EfficientNet-lite, the calculation amount is only 230Mflops(0.23Bflops), and the model size is 1.3MB

yolo_tensorflow

Tensorflow implementation of YOLO, including training and test phase.

yolo_tensorflow-1

tensorflow implementation of 'YOLO : Real-Time Object Detection'