Comments (2)
Now there are known bugs in RegisterFile and some other modules, so maybe simulation error is not because of your simulator backend. After fixing them we'll test other simulator backend.
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Now VCD files can generate successfully with Treadle backend.
Now there are known bugs in RegisterFile and some other modules, so maybe simulation error is not because of your simulator backend. After fixing them we'll test other simulator backend.
from ventus-gpgpu.
Related Issues (20)
- Environment setting for ventus HOT 2
- 你好,请问当前版本实现了MMU了吗? HOT 2
- make verilog编译报错:1 targets failed HOT 1
- make verilog编译报错 HOT 5
- CUDA中的三维网格、线程块如何映射到硬件? HOT 6
- make tests出错
- support FPGA? HOT 11
- When run make test, it occur with the following message. Mill version is 0.10.8. HOT 1
- When we use command "make compile", here report the following errors: val config = chipsalliance.rocketchip.config HOT 1
- Where can I configure the number of cores? HOT 1
- 【RFC】关于ventus的gnu工具链支持 HOT 1
- Chisel 3.6+ Support HOT 2
- make test报错 commit: 19dc44a7529198411a7ed5b17d19443d545bddd2 HOT 1
- saxpy2 test error HOT 4
- Cannot use the released version "VENTUS-2.0.2" of software part HOT 2
- fpga_test HOT 1
- done
- 关于承影的正确性验证 HOT 2
- It seems PCcontrol.scala in dev_issue branch has compile error HOT 2
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