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adaptagrams

Libraries for constraint-based layout and connector routing for diagrams.

antlr4

ANTLR (ANother Tool for Language Recognition) is a powerful parser generator for reading, processing, executing, or translating structured text or binary files.

cocotbext-ahb

Cocotb AHB Extension - AHB VIP

elkjs-svg

grammars-v4

Grammars written for ANTLR v4; expectation that the grammars are free of actions.

hdlconvertor

verilog and vhdl parser module for python

jinja

A very fast and expressive template engine.

midi_synthfpga

Sound synthetizer with an fpga

myhdl

The MyHDL development repository

nanobind

nanobind — Seamless operability between C++17 and Python

planarity

Planar graph algorithms

sd_spi

SPI / SDCard through serial controler experiment

sdcard-pg

SD Card play ground

surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API.

sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

uhdm

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

verilog-arbiter

A look ahead, round-robing parametrized arbiter written in Verilog.

weasyprint

The awesome document factory

zia

ZIA Code Repository

zpuino-hdl

ZPUino HDL implementation