How to enable scattered mode in fastclick? about fastclick HOT 7 CLOSED

It's currently not supported. It would be easy to enable, but then:

• either scattered buffers would end up in a different Packet objects (one per buffer). The second packet and subsequent would therefore look like garbage. Unless your pipeline is very simple it's not viable.
• we skip all "subsequent buffers" and only integrate the first buffer with the header as a Packet object. Internally, the subsequent buffers will be linked by DPDK but that will not be exposed to FastClick elements that will see a 64B packet. Therefore elements cannot access the payload of the "silently linked lists" buffers but it will be transmitted as one if forwarded to a DPDK Device.

Even if we imagine providing real support, it would lead to a general performance drop. We'll have to handle batches of linked lists of packets instead of batches of packets everywhere. Many "unlikely" conditions everywhere just for the scattered case...

A simple handling would be to copy scattered packets to a unique buffer, but that'll drop performance of course.

The best course of action would be for Mellanox to send packets to different queues according to their size (like the Tilera they acquired), so we could have queues with different buffer size.

What's the use case?

from fastclick.

I was inspired by the eurosys19 paper（make the most use of the last level cache）. And I try to send the packets larger than 64B all to one slice.

from fastclick.

Ah we had discussed that with @aliireza of course , and I think he never advanced towards that for the reason above. The cost of handling scattered packets is huge. That's also why LRO and GRO is used everywhere: it's much better to concatenate payload, even at the cost of zero-copy, than handling more packets/buffers/etc.

Remember a rte_mbuf is 2 cache lines and the second one can't even go to the right slice. So for the few ns of L3 slices you gain, handling many many more descriptors is not worth it. I think it would be more efficient to ask Intel to provide a way to define the cache mapping exactly :p (Way beyond ways of DDIO).

from fastclick.

Thanks a lot for your suggestion, so all I wanted to do was test how much performance overhead it would be.

from fastclick.

I also think your method is the most reasonable one at the moment for the use of NUCA properties. However, I also want to measure how much performance loss other methods have, so I want to turn on the scattered mode in fastclick.

from fastclick.

I'll close the issue because right now it's not supported.

We can discuss ways to implement something though. Maybe we can discuss this offline? [email protected]

from fastclick.

Okey

from fastclick.