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neha-pqs avatar neha-pqs commented on September 27, 2024 1

Ah, right. I now see what you had in snapshot. Apologies.
I will debug why I dont get same behaviour.
Thank you for confirming that VIP supports it.

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taichi-ishitani avatar taichi-ishitani commented on September 27, 2024

Hi @neha-pqs ,

This feature has already been supported.
You can generate such access by setting write_data_delay[0] smaller than start_delay.

rand int start_delay;

rand int write_data_delay[];

image

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neha-pqs avatar neha-pqs commented on September 27, 2024

Hello,

In the snapshot you have attached, awvalid and wvalid assert at the same time but my request is for wvalid -> awavlid.
I see the same behaviour as your waves.

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taichi-ishitani avatar taichi-ishitani commented on September 27, 2024

This write request is the 1st request on the simulation.
Therefore, this snapshot shows that wvalid assertion before awvalid assertion.

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taichi-ishitani avatar taichi-ishitani commented on September 27, 2024

You said the access pattern that all write data are transferred and then awvalid is asserted?

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neha-pqs avatar neha-pqs commented on September 27, 2024

I am talking about this from AMBA spec:

image

I can send you a waveform snapshot tomorrow from my sims if you like.

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taichi-ishitani avatar taichi-ishitani commented on September 27, 2024

write address for write data at 1st console is write address at the 2nd console.
therefore, the above snapshot shows this pattern.
image

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