Comments (2)
I am not aware of a mechanism using SystemRDL's built-in properties that would allow you to describe this behavior.
I would suggest requesting this feature here: https://forums.accellera.org/forum/52-systemrdl-discussion/
Hopefully Accellera can add something to the official spec in the next revision.
Alternatively, SystemRDL's User Defined Properties (UDPs) could be used to describe this construct, and support added to this code generator.
from peakrdl-regblock.
I am not aware of a mechanism using SystemRDL's built-in properties that would allow you to describe this behavior.
I would suggest requesting this feature here: https://forums.accellera.org/forum/52-systemrdl-discussion/ Hopefully Accellera can add something to the official spec in the next revision.
Alternatively, SystemRDL's User Defined Properties (UDPs) could be used to describe this construct, and support added to this code generator.
Thanks.
I think external register could be used for this purpose.
from peakrdl-regblock.
Related Issues (20)
- Interface data width vs register width vs access width HOT 1
- Unaligned external addressable components
- Clock gating support HOT 4
- More optimized readback stage RTL generation HOT 3
- Put pragmas around assertions HOT 2
- Parity on R/W registers HOT 2
- Fine-grained access rights HOT 2
- [FEATURE] External register fields HOT 1
- [BUG] memory size is not calulated correctly HOT 4
- External registers packed struct HOT 1
- [FEATURE] Parameters in regblock package
- [BUG] Genus unsynthesizable error on rising/falling edge interrupt field
- Saturating counters perform inequality check twice in generated logic
- [BUG] reg after external mem is only generated if not in regfile or addrmap
- [BUG] Incorred bit extraction on external component address assignment
- SW = rw, HW = rw behavior seems incorrect HOT 3
- Files generated by this project do not work with Verilator HOT 3
- Timing of swmod seems 1 cycle too early HOT 2
- External mem state machine gets confused by rd_ack that may result from READ_FIRST BRAMs HOT 3
- hwset on multibit field HOT 5
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