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aarch64cryptolib

AArch64cryptolib is a from scratch implementation of cryptographic primitives aiming for optimal performance on Arm A-class cores

armv8_crypto

dma

Linux UIO Driver for AXI DMA

fpga-peripherals

:seedling: :snowflake: Collection of open-source peripherals in Verilog

hardware-implementation-of-aes-verilog

Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog

hardware-implementation-of-aes-vhdl

Hardware Implementation of Advanced Encryption Standard Algorithm in VHDL

hlx_examples

Open Source HLx Examples

iiot-eddp

The repository contains the design database and documentation for Electric Drives Demonstration Platform

kvcordic

Multi-function, universal, fixed-point CORDIC

linux-xlnx

The official Linux kernel from Xilinx

no-os

Software drivers in C for systems without an operating system

oh

Silicon proven Verilog library for IC and FPGA designers

parallella-fpga-dummy-io

Sample minimal Vivado project for Parallella FPGA

sdram-controller

Verilog SDRAM memory controller

stm32-usart-uart-dma-rx-tx

STM32 examples for USART using DMA for efficient RX and TX transmission

stm32f103-keil

udmabuf

User space mappable dma buffer device driver for Linux.

verilog-uart

Verilog UART

vsdflow

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.

xilinx_axidma

A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.

zephyr

Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.

zynq7000